Novel Package Structure for Enhancing Power Integrity Performance & Cost Efficiency

A novel approach to enhance power integrity performance in flip chip molded packages is proposed by implementing power and ground planes directly onto the mold layer. The design involves copper (Cu) sputtering power planes onto the first molded layer, followed by a second mold layer for the ground. This novel structure introduces several key benefits in terms of power integrity, cost, and manufacturing efficiency, making it a promising solution for high-performance semiconductor applications. Typical flip chip packages require multiple internal metal layers within the substrate to route power and ground connections which increases the overall layer count, production complexity, production times, and cost. The solution simplifies the package architecture by eliminating several internal routing layers and instead utilizes the external mold surface to carry the power and ground planes. This results in a reduced layer count within the substrate. A significant feature of this approach is the proximity of the power and ground planes. Positioning these planes close together on the mold surface increases the inherent capacitance between them. The higher capacitance acts as a built-in decoupling capacitor, reducing high-frequency noise in the power distribution network (PDN). The increased capacitance helps stabilize the PDN, leading to improved power integrity and overall system reliability. Sputtering conductive planes directly onto the mold achieves optimized impedance characteristics by lowering parasitic inductance and resistance, both of which are critical factors in maintaining efficient power delivery in high-frequency applications. In terms of manufacturing, this design offers several advantages. Sputtering to deposit power and ground planes on the mold surface eliminates the need for a complex multi-layer substrate manufacturing process, thereby reducing material usage and the number of processing steps. This translates to lower production costs and shorter cycle times. The elimination of additional substrate layers not only simplifies the design but also contributes to a more compact package, making it suitable for applications where space is at a premium. Electrical simulation results have demonstrated the effectiveness of this structure in maintaining robust electrical performance, particularly in the reduction of impedance in the PDN. Additionally, the reduction in layer count simplifies the overall package structure, leading to a decrease in both material and production costs while improving manufacturing throughput. This new approach has the potential to offer substantial improvements in the design of compact, high-performance semiconductor packages.