Automated Multi-Physics Reliability-Oriented Layout Design for Multi-Chip Power Modules Using the LAREL Tool

As electrification advances across various industries, the need for multi-chip power modules (MCPMs) with higher power densities continues to grow. These modules play a crucial role in power electronics applications such as electric vehicles (EVs), renewable energy systems, and industrial automation, where efficiency and compact designs are paramount. However, MCPMs are exposed to increasingly harsh operational environments—featuring high temperatures, mechanical stresses, and heavy electrical loads—making long-term reliability a critical concern. Failures in MCPMs can result in significant system downtimes, reduced energy efficiency, and safety risks, particularly in critical sectors like transportation and energy. To address these challenges, layout optimization becomes essential. PowerSynth, an in-house design automation tool developed at the University of Arkansas, focuses on reducing loop inductance and predicting maximum junction temperatures in MCPMs [1]. However, while effective in optimizing key parameters, PowerSynth does not fully evaluate the reliability of wire interconnections, which are essential for long-term performance [1]. To bridge this gap, we developed the Layout Reliability Tool (LAREL), which integrates with PowerSynth to automate the extraction of MCPM component stress and temperature data from ParaPower [2], excluding wire interconnections. LAREL extends PowerSynth’s capabilities by assessing wire bonds and interconnection points through detailed data on stress and temperature [3]. This assessment helps evaluate critical factors such as electromigration and mechanical stress, both of which are crucial to MCPM reliability [3]. The process of optimal layout identification with LAREL occurs in two stages. In the first stage, LAREL evaluates each layout based on maximum wire inductance and minimum wire lifetime, providing a clear comparison of layouts for further refinement. By incorporating electromigration-stress models and industry-standard wire inductance calculations (JESD 59) [3][4], LAREL allows designers to effectively rank MCPM configurations, ensuring the selection of the most reliable layouts for continued optimization. In the second stage, LAREL utilizes user-defined wire feature ranges to generate a wider spectrum of design variations. Monte-Carlo sampling is employed to explore both discrete and continuous values within these ranges [2]. The generated values feed into a multi-objective optimization algorithm, Strength Pareto Evolutionary Algorithm 2 (SPEA2) [5], which refines wire interconnection designs to balance competing objectives such as reducing wire inductance while enhancing wire lifetime. This process generates an optimal Pareto front, guiding the selection of the best layout in terms of both performance and reliability. Although the tool’s evaluation in this study focused on reliability and inductance, LAREL’s flexibility allows for the use of user-defined failure or performance models, making it adaptable for other specific application needs. By incorporating reliability metrics in both the layout selection and detailed optimization phases, LAREL enables a holistic evaluation of MCPMs under operational stresses. Its automated workflow—from layout extraction to reliability evaluation and re-optimization—provides a faster, more reliable design process for MCPMs. The significance of this work lies in bridging the gap between layout optimization and reliability evaluation, empowering designers to make informed decisions about MCPM layouts and interconnections [1]. As power densification remains a critical goal, LAREL’s automated, multi-faceted approach ensures next-generation MCPMs meet stringent reliability and performance demands, advancing the future of power electronics.