Development of a High-Density Adaptive Redistribution Technology for Embedded High I/O Components

The growing demand in the industry for high-performance electronic devices that offer enhanced functionality, reduced power consumption, and increased speed is fueling innovation in advanced packaging technology. Enhancing semiconductor chip performance and advancing package features are essential. One approach to producing high-performance electrical systems that meet compute-intensive requirements in space-constrained products is to use miniaturized packages with advanced embedded components. In addition to ensuring sufficient yield from the lithographic process to maintain high density and preserve valuable components, a key aspect of RDL formation is accurately aligning each layer of the production board with the corresponding component during lithography. A viable solution is to measure the deviation between the target and actual positions, digitally recalculate and reroute the interconnects in the RDL pattern, and then process the adjusted data into a raster image format for a maskless direct imaging process. The paper presents results from the EU-funded CHARM project, in which AT&S supplied FHG IZM with embedded components measuring 26 mm x 18 mm x 110 µm. During the embedding process, build-up (BU) polymer resin (ABF®) material was used to symmetrically embed temporarily fixed components using a carrier. After exposing the copper pillars (30 µm diameter) through the BU film, a PVD technique was used to deposit titanium and copper on the surface. To connect the embedded components, IZM developed an adaptive patterning process that includes an optical measurement routine and software to digitally correct the manufacturing data. The corrected data is then fed into a maskless lithography tool, ensuring that each unique device on each panel is accurately registered. In addition, results will be presented on how the semi-additive process (SAP) can be improved by using an enhanced direct imaging process on an embedded die to achieve a resolution of 5 µm L/S despite the challenges posed by topography and surface roughness. Furthermore, this paper briefly discusses the development of the essential technology blocks for high-density redistribution layers required for the realization of organic substrate-based packages. The chosen technological approach is advanced semi-additive processing (aSAP) on a large scale. This method includes the use of dielectric layers such as ABF or similar materials, PVD seeding and additive electrolytic copper deposition. It also describes the application of thin PVD seeding layers below 50 nm and the incorporation of plasma processes for dry etching of photoresists, surface cleaning and back etching of seed layers on 610 mm x 457 mm panels.