Warpage Evaluation in Embedded Bridge Package for Advanced Package Solutions

As the influence of artificial intelligence (AI) continues to grow, it shapes the future of advanced packaging by enabling smarter designs and adaptive manufacturing processes that address emerging challenges. Advanced packaging through chiplet integration offers significant value for applications that demand high performance and high-density requirements, such as AI, high performance computing (HPC), and data centers. One of the novel advanced packaging platforms for this solution is the fan-out embedded bridge technology. This technology integrates multiple chiplets with diverse functions into one single package using a small silicon (Si) bridge die which is embedded in the fan-out organic redistribution layer (RDL) interposer layers. This design enables ultra-high-density die-to-die (D2D) connections with line/space (L/S) dimensions of less than 1/1 um. In addition to providing flexibility in Si bridge and L/S design selections for various applications, this technology is also more cost-effective than 2.5D Si Interposer package with through-silicon via (TSV) structure. Moreover, this bridge technology facilitates the integration of other components by strategically embedding it beneath the active die for die-to-die interconnects or embedded power modules. In this paper, we will explore the warpage behavior on complex integration of embedded bridge technology with and without embedded power module components. Both Si bridge die and the power components have small, and thin structures with various thicknesses, presenting challenges during package assembly processes that can exacerbate warpage on top of existing chiplet integration in embedded bridge technology. High warpage result, which is typically measured using the Shadow Moiré technique on finished chip module (CM) may lead to possible defects during assembly process, like non-contact open, bridge, non-wet or stretch joint. These issues can lead to failures at time-zero and during reliability tests. Additionally, we will analyze various warpage behaviors and performance scenarios through simulations that involve only Si bridge dies, and power components in conjunction with Si bridge dies. Finally, this paper elaborates on methods to control warpages to ensure high-quality integration, which is crucial for outsourced semiconductor assembly and tests (OSATs).