Investigation of Behavior of Nanovoids in Electroless Cu Layer of 1st via Bottom of 3-Layer Stacked Micro-via Integrated in Substrate under Thermal Shock Test

The HDI-PCB consists of multiple interconnecting layers, mainly connected by micro-vias or through holes, therefore, micro-vias are very important because they enable cost-effective miniaturization of complex high-frequency circuit designs and provide high input/output (I/O) to the package board. Micro-vias are usually copper connections and are formed by plating. For this reason, the micro-via connections form a three-layer structure consisting of electrolytic copper-plated vias/electroless copper-plated layers/electrolytic copper-plated wiring layers. Unlike electrolytic copper plating layers, which are formed by electrochemical reactions, electroless copper plating layers are formed only by chemical reactions, but because of this, the electroless layer forms a copper-copper bonding interface containing many impurities such as additives and stabilizers, and the residual organic might remain after desmear process. As a result, cracks, and delamination at the micro-via interface are more likely to occur, degrading the quality of micro-via and causing reliability problems, a “Weak Interface Micro-via Failure”1-2). Normally, in the electroless copper plating process, the reduction of copper (Cu) ions and the oxidation of the reducing agent of formaldehyde (HCHO) reaction occur and hydrogen (H2) is generated during the reaction. This hydrogen is discharged into the bath and partly incorporated during electroless plating. The generated hydrogen is incorporated into the electroless plating layer and forms nano-sized voids (nanovoids) during plating or by subsequent heat treatment3-4). As micro-via failures occur at the micro-via bottom interface, it is important to analyze the behavior of nanovoids and the elemental quality of the electroless Cu layer during the reliability tests. Firstly, we conducted FEM simulation of a three-layer stacked micro-via structure to analyze the stress distribution under high and low temperatures. The maximum stresses are primarily located at the bottom of the micro-via structure, where the electroless Cu deposition occurs. Next, we carried out a scanning transmission electron microscopy (STEM) analysis for the bottom of the micro-via, where the maximum stresses are primarily located as shown by FEM simulation, of a three-stacked micro-via structured with two prototype substrates, including two kinds of micro-vias structures, one using the conventional electroless plating process (traditional sample)1) and another using the OPC-FLET electroless plating process (OPC-FLET sample ) after performing a thermal cycle test. A STEM observation and an elemental analysis for the two types of electroless layer of the micro-via. In traditional samples, nanovoids are found inside the electroless Cu plating layer itself. These nanovoids, formed during electroless plating, grew due to the thermal cycle treatment, and new voids have also arisen at grain boundaries. During the thermal cycle test, the stress due to the resin’s continuous expansion and contraction concentrated at the bottom of the macro-via, it can be thought that nanovoid formation and growth are enhanced due to thermal and stress induction. In OPC-FLET samples, nanovoids are found similar to the traditional sample but the size of them are rather small, These nanovoids, however, smaller in size and fewer in number, might grow and connect into submicron-sized voids or cracks, leading to the failure of micro-vias but it takes more time to reach failure in the case of the OPC-FLET sample. The result of FEM simulation suggests that a poor electroless layer might pose a potential risk for the failure of the micro-via structure. The results of STEM characterization show the behavior of nanovoids in an electroless plated layer prepared with two kinds of electroless Cu plating processes under the thermal cycle test and suggest that the possibility of failure at the bottom of the micro-via with the OPC-FLET method might be lower than that with the traditional one.