MERINDA: Model Recovery in FPGA-Based Dynamic Architecture for Edge and Physical AI

Understanding the physical laws that govern real-world data is fundamental to achieving safe and explainable operation of mission-critical autonomous systems (MCAS)—a cornerstone of physical AI. Model Recovery (MR) serves as a key mechanism for inferring governing equations directly from data. However, deploying MR within MCAS must contend with stringent latency, computational, and power constraints, making edge-AI acceleration essential. Field-Programmable Gate Arrays (FPGAs) provide an attractive hardware substrate due to their reconfigurability and real-time processing capability. Yet, existing MR techniques often rely on computationally intensive nonlinear optimization or the numerical solution of multiple ordinary differential equations (ODEs) embedded within neural architectures, leading to high compute and memory overheads. To address these challenges, this article introduces MERINDA (Model Recovery in Dynamic Architecture), an FPGA-accelerated MR framework that integrates Gated Recurrent Units (GRUs) with an invertible mapping parameterized as a linear combination of nonlinear basis functions. We theoretically establish that MERINDA is functionally equivalent to Neural Ordinary Differential Equation (NODE)-based MR architectures, while eliminating the need for repeated ODE integration during training and inference. Empirical evaluations on benchmark datasets against Extracting sparse Model from ImpLicit dYnamics (EMILY), Sparse Identification of Nonlinear Dynamics (SINDY), and Physics-Informed Neural Networks with Sparse Regression (PINN+SR) demonstrate that MERINDA achieves comparable accuracy with substantial gains in processing speed, energy efficiency, and DRAM utilization. We further analyze the energy–memory tradeoff in MERINDA, showing that optimizing one resource directly impacts the other under fixed accuracy constraints. Using mixed-integer programming, we derive resource-aware optimal hyperparameters and construct the Pareto front that compares FPGA edge deployment against Mobile GPU (M-GPU) and server-class Graphics Processing Units (GPU) platforms. Our results highlight MERINDA’s energy efficiency, reduced training time, and smaller memory footprint, reinforcing its viability for deployment in resource-constrained autonomous systems.