Efficient Interleaver Architecture for Modern Global Navigation Satellite Systems

In modern Global Navigation Satellite Systems (GNSS), interleavers are essential for improving system performance. However, limited research has focused on interleaver hardware optimization specifically for GNSS, primarily due to GNSS authorities strictly adhering to Interface Control Documents (ICDs), which discourage significant deviations in hardware implementations. Traditional GNSS interleavers employ double buffering and typically require extensive hardware resources, specifically 2N registers and 2(N− 1) + 1 multiplexers (MUXs), leading to increased complexity, power consumption, and latency. To bridge this gap, this paper presents a novel and efficient interleaver hardware architecture optimized specifically for modern GNSS by leveraging Lifetime Analysis and Forward–Backward Register Allocation. Lifetime Analysis precisely identifies the minimum number of registers necessary, and Forward–Backward Register Allocation ensures efficient utilization of these resources under continuous operation. Experiments were conducted for all seven currently used GNSS interleaving configurations. Synthesis results, obtained using a standard 28 nm Complementary Metal-Oxide Semiconductor (CMOS) process, demonstrate significant reductions in chip area (38.82% reduction), power consumption (52.01% reduction), and latency (25.05% improvement) compared to conventional architectures. These benefits become increasingly critical as the interleaver data length N continues to grow, providing a practical, ICD-compliant solution for resource-constrained satellite payloads and receiver designs.