Two-Dimensional Dynamic Logic Resource Allocation for Scalable RIS Channel Emulation

This paper addresses the critical scalability challenge in Hardware-in-the-Loop (HIL) channel emulation for massive RIS-assisted 6G environments. We propose a Two-Dimensional Dynamic Logic Resource Allocation (2D-DLRA) architecture that decouples physical RF ports from baseband processing resources through hierarchical pooling at both the session level and the multipath level. By jointly virtualizing Logical Units (LUs) and Multipath Processing Units (MPUs), the proposed architecture overcomes the dual inefficiency of port underutilization and path-level sparsity inherent in conventional static designs. A rigorous analytical framework combining hierarchical queuing theory and non-cooperative game theory is developed to characterize system capacity, blocking probability, and user contention under heterogeneous workloads. Simulation results demonstrate that, under a strict QoS constraint of 1% blocking probability, the proposed 2D-DLRA architecture achieves a multi-fold increase in supported user capacity compared to static allocation with the same hardware resources. Moreover, for an end-to-end emulation error threshold of 3%, 91.8% of users meet the QoS requirement, compared to only 73.6% in static architectures. The results further show that dynamic pooling enables near-saturated hardware utilization, in contrast to the single-digit utilization typical of static designs in sparse RIS scenarios. These findings confirm that 2D-DLRA provides a scalable and hardware-efficient solution for large-scale RIS channel emulation, offering practical design guidelines for next-generation 6G HIL testing platforms.