A 3.3‐dBm 31% Efficiency IoT Transmitter Employing Harmonic‐Rejection PA With −$$ - $$57‐dBc HD3 and −$$ - $$62‐dBc HD5

ABSTRACT This paper presents a wideband transmitter for Internet of Things (IoT) applications, featuring an open‐loop binary frequency‐shift keying (BFSK) modulator and a proposed harmonic‐rejection switched‐capacitor power amplifier (HR‐SCPA). The BFSK modulation is implemented using a phase multiplexer driven by 16‐phase carrier signals generated from a delay‐locked loop (DLL), enabling high data‐rate modulation without the bandwidth limitations of traditional PLL‐based architectures. To mitigate spurious emissions, a pseudorandom phase transition (PRPT) scheme is introduced, offering improved effective phase resolution and higher spectral efficiency compared with delta–sigma modulation (DSM)–based randomization. Furthermore, the proposed HR‐SCPA employs multiphase square‐wave control signals to shape the output waveform and effectively suppress the third and fifth harmonics. The TX is designed using a 65‐nm CMOS process with a core area of 0.0477 . It achieves harmonic rejection of 57 and 62 dBc for the third and fifth harmonics at 1 GHz. It delivers 3.3‐dBm output power with 31% system efficiency and a power consumption of 6.8 mW. The design supports carrier frequencies from 0.8 to 1 GHz and data rates ranging from 1 to 15 Mb/s.