Impact and Optimization of ZnSe Buffer Layer Thickness and Doping on CIGS Solar Cell Efficiency: A TCAD-based Study

Copper indium gallium selenide (CIGS) solar cells are among the most efficient thin-film photovoltaic technologies due to their high absorption coefficient, long-term stability, and bandgap tunability. However, the conventional CIGS/CdS structure raises environmental and regulatory concerns associated with cadmium toxicity, driving the development of fully Cd-free device architectures. In this context, zinc selenide (ZnSe) is a promising alternative buffer layer owing to its wide bandgap, high transparency, and favorable band alignment with CIGS. This work numerically investigates the combined influence of ZnSe buffer-layer thickness and doping concentration on the electrical performance of CIGS solar cells using the ATLAS-SILVACO TCAD simulator. The key photovoltaic parameters examined include the short-circuit current density (JSC), the open-circuit voltage (VOC), the fill factor (FF), and the power conversion efficiency (η). The results show that ZnSe thickness has a limited impact on VOC but significantly affects JSC, FF, and η. Very thin layers exhibit higher interfacial recombination and incomplete junction formation, whereas an optimal thickness between 0.08 and 0.10 µm ensures improved carrier transport, reduced losses, and superior efficiency. Doping concentration also plays a determining role. Although JSC and VOC remain only weakly sensitive to doping, the FF and η degrade markedly at high doping levels due to increased defect density, reduced carrier mobility, and enhanced nonradiative recombination. The optimal doping range is found to be 8×10<sup>16</sup> to 2×10<sup>17</sup> cm<sup>-3</sup>. Overall, the study provides clear guidelines for optimizing ZnSe-based buffer layers and demonstrates the importance of jointly controlling thickness and doping to design high-performance, environmentally compliant Cd-free CIGS solar cells. These results also offer a robust numerical foundation for future experimental validation and further device optimization.