Analysis and design of aging-resistant strategies for TCFF

With the increasing demand for energy-efficient chips, various low-power flip-flops have been developed. Among these, TCFF has attracted significant attention for its ability to achieve low power consumption while maintaining overall performance. However, under advanced process technologies, TCFF faces challenges such as increased delay and potential functional failures caused by device aging. This paper proposes an anti-aging strategy for TCFF to address these challenges, leveraging the synergistic optimization of structural modification and Transistor size adjustment. Results demonstrate that TCFF exhibits reduced delay degradation across all corners. In particular, under the FF corner, the delay degradation of the rising and falling edges is mitigated by 19% and 12%, respectively. Moreover, the power-delay product (PDP) of TCFF increases by only 3.7%, while its static power consumption shows a slight reduction.