DTCO-based Hybrid Rail 8T Complementary FET SRAM Design towards advanced node

As technology scaling advances toward the sub-1nm era, Complementary Field-Effect Transistor (CFET) architectures offer a promising path to sustain SRAM density and performance. The inherent 3D integration capability of CFET technology proves particularly advantageous for implementing 8T SRAM configurations at advanced nodes, overcoming the structural limitations of conventional 6T designs. However, the footprint of the current 8T CFET SRAM is still much larger than 6T SRAM. This work proposes a CFET-compatible hybrid-rail 8T SRAM design that addresses interconnect and layout challenges, achieving a 27% reduction in cell area compared to conventional dual-port 8T CFET SRAM. Furthermore, it demonstrates reduced parasitic effects on the bitline (BL) and wordline (WL). Through a Design Technology Co-Optimization approach (DTCO), SPICE simulations reveal that the hybrid-rail 8T SRAM achieves significant improvements in terms of power and delay. The results show that hybrid-rail 8T SRAM offers superior area efficiency, energy savings, and performance, establishing it as a compelling solution for high-density, low-power memory in advanced-node applications.