Total Ionizing Dose Effect Simulation Study on 130 nm CMOS Processor

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor's failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors.