Numerical Simulation Study and Design Optimization of High-Performance SiGe/Si Heterostructure Nanowire Tunnel FETs

Abstract Conventional silicon-based tunneling field-effect transistors (TFETs) face several issues, including limited ON current, ambipolar conduction, and suboptimal RF performance. This simulation-based study presents a detailed design and optimization approach for a high-performance heterostructure nanowire tunneling FET (NW-TFET). Starting from a fabricated baseline NW-TFET structure, we modify the design through a series of optimization phases to improve both DC and radio-frequency (RF) characteristics. The proposed design features a heterojunction structure in which the source region is composed of Si 1-x Ge x to enhance the tunneling probability, thereby increasing the ON current. The design also includes the integration of a 15 nm HfO 2 pocket, careful tuning of gate-source alignment, and optimization of the x-composition in the source. Extensive simulations show significant improvements in ON current (I ON ), ON/OFF current ratio, subthreshold swing, and cutoff frequency ( $${f}_{T})$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:msub> <mml:mi>f</mml:mi> <mml:mi>T</mml:mi> </mml:msub> <mml:mrow> <mml:mo>)</mml:mo> </mml:mrow> </mml:mrow> </mml:math> compared to the initial configuration, with x = 0.75, 0.5 nm pocket underlap, 50 nm gate length, $$60\text{ nm}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mn>60</mml:mn> <mml:mspace/> <mml:mtext>nm</mml:mtext> </mml:mrow> </mml:math> channel length and work function of 4.3 eV. The optimized device achieves an ON/OFF ratio of 4.79 × 10 6 , a subthreshold swing (SS) of 64.5 mV/decade, threshold voltage ( $${V}_{t})$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:msub> <mml:mi>V</mml:mi> <mml:mi>t</mml:mi> </mml:msub> <mml:mrow> <mml:mo>)</mml:mo> </mml:mrow> </mml:mrow> </mml:math> of 0.253 V and a maximum cutoff frequency of 355 GHz, while keeping ambipolar current low. These findings highlight the potential of the proposed NW-TFET architecture for low-power, high-speed applications.