Charge Trapping Dynamics of Nanofloating Gates in Synaptic Transistors Revealed by Genomic Simulation for High-Performance Neuromorphic Device Design

Neuromorphic hardware integrates computing and memory with parallelism and ultralow power, offering a promising solution to overcome the von Neumann bottleneck. Artificial synapses are critical components; however, directly observing microscopic electron distribution gradients and their dynamic evolution remains challenging, hindering charge storage understanding and device optimization. This study employed quantum dot (QD) floating-gate synaptic transistors as a model, leveraging high-throughput, high-precision simulations to systematically explore the mutual effects of QD size, QDs' concentration gradients, and carrier concentration fields. The simulations revealed dynamic evolution of charge trapping behavior, transitioning from shallow trap coupling collapse to network-like migration and deep-level localized trapping as the device genome shifted. Simulation-based screening identified high-performance device genome modules, enabling the design of a bilayer different scales QD array device with a specific "gene combination". This device achieved 96.95% MNIST recognition accuracy, a 4.72% improvement over monolayer structures, with optimized charge-trapping depth and retention. These findings demonstrate that high-throughput, high-precision device genome simulations provide an efficient pathway for developing high-performance neuromorphic hardware and systems by establishing gene-performance mapping models.