Diagnostic des défauts par les techniques d'intelligence artificielle et commande tolérante aux fautes pour une chaine de traction véhicule électrique à base d'une machine synchrone à rotor bobiné

Driven by the need for lower emissions and higher energy efficiency, recent innovations in transportation have significantly advanced electric drivetrain technologies. Wound rotor synchronous machines (WRSMs) have gained attention as a rare-earth-free, energy-efficient alternative for urban electric vehicles, especially effective at high speeds. Ensuring drivetrain reliability, however, requires fault detection and isolation and integrated design strategies that address safety, performance, and long-term durability. This doctoral dissertation aims to develop fault detection and diagnosis monitoring strategies based on artificial intelligence techniques, along with fault-tolerant control strategies for electric vehicle (EV) powertrains equipped with WRSMs. First, an EV powertrain simulator was developed based on the analytical WRSM model, and various control strategies were evaluated under healthy operating conditions using the Worldwide harmonized Light vehicles Test Cycle. A loss-minimization control strategy and a robust speed loop were proposed to improve energy efficiency and dynamic performance. Second, a real-time data-driven diagnostic framework was introduced to address open-circuit faults in the inverter, integrating supervised machine learning with an adaptive sliding window approach. This method dynamically adjusts the window size according to the current signal's time-varying characteristics, enabling effective detection of nonstationary faults while reducing diagnostic latency. Third, passive velocity observers based on the extended Kalman filter and sliding mode observers were developed for WRSMs, which are capable of operating under medium-to-high speed and variable load torque conditions, thereby enabling sensor fault-tolerant control. All proposed methods were validated through Simulink-based simulations and hardware-in-the-loop test bench experiments.