Modified vedic multiplier architecture using Nikhilam and Karatsuba algorithms with hybrid adders for enhanced performance

High-performance computing applications rely on efficient multipliers, such as Digital Signal Processing (DSP) and Machine Learning (ML). This paper proposes an optimized 8 × 8 multiplier architecture by utilizing a Modified Vedic Nikhilam(VN) Sutra with a Modified Karatsuba Algorithm (KA) in order to increase speed, lower power consumption, and reduce complexity. The design will be equipped with hybrid adders with a Fast Carry Switching Adder (FCSA) and Kogge-Stone Adder (KSA) for carry propagation, as well as latency improvements.Synthesized onaXilinx Spartan-3E and reprogrammed with a KP2 (team analog) device, the proposed architecture achieved a 30% speed improvement and a 25% reduction in power consumption from conventional (standard) Vedic Multipliers (VMs). The Modified VN Multiplier operates with a delay of 27.95 ns at a power consumption of 248.93 mW.In comparison, the Modified Karatsuba design operates with a delay of 25.79 ns and a power consumption of 293.65 mW. The combined architecture has a Power Delay Product (PDP) of 7270 pJ, which will yield substantial improvement from Wallace, Dadda, and VMs. The proposed architecture is well-suited for many low-power, maximum-speed applications in real-time signal processing and embedded systems. Future implementations aim to scale the design up to 32-bit and 64-bit operations to validate its effectiveness for high-performance computing applications.