Design the Power Evaluation of a Highly Efficient Low-Complex Adder Implementation Using Inequality Gate by Quantum-Dot Cellular Automata

Quantum dot cellular automata (QCA) is one of the technologies in development for building VLSI circuits at the nanoscale. It has promising advantages over other existing technologies, with parameters like area in micrometers, power consumption in the order of micro to nanowatts, and the circuits being operated at terahertz frequency. Fundamentally, an Adder is the basic unit to design any digital arithmetic and logic circuits. In this work, we have proposed the power dissipation analysis of an adder circuit with highly efficient, low complexity, and less latency. The required area, and power are also calculated. The Adder was constructed using an inequality gate by considering 13 quantum cells. The design occupies an area of 0.02 μm2. It is reduced ten times from the original, and the delay is reduced from 4 clock cycles to 0.25 clock cycles. The delay is reduced by sixteen times. In this work, the power dissipation analysis is proposed and is calculated as 2.410 for 19 cell adder and 1.4639 nanowatts for 13 cell adder. The layout simulation is done using QCADesigner 2.0.3, and these results are compared to the existing methods. These modules exhibited excellent performance in various parameters, less area utilization, fewer quantum cells for the circuit, low latency, and power dissipation.