Indium-Gallium-Zinc Oxide Thin-Film Transistor Optimization for Memristive Applications

Metal-oxide resistive random-access memory (RRAM) offers strong potential for emerging memory and computing, particularly when integrated into crossbar arrays for in-memory processing. Scalable array operation nonetheless depends on pairing each RRAM element with a well-optimized switching transistor. Given the large selection of metal oxide RRAM materials and delicate power requirements for processes such as electroforming, switching and current limiting, the transistor must be finely optimized for enabling a functional crossbar array. This work defines key criteria for thin-film transistor (TFT) used as switching elements in resistive memory, focusing on high drive current and ultralow <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state current. An optimized IGZO TFT process is presented, where a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$350~^{\circ } $</tex-math> </inline-formula>C post-annealing yields an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$681~\mu $</tex-math> </inline-formula>A, enabling reliable operation of a TiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <i>x</i> </sub> one-transistor one-resistor (1T1R) cell. A three-channel architecture reduces the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state current from 3×<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10}^{-{7}}$</tex-math> </inline-formula> A to 1×<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10}^{-{13}}$</tex-math> </inline-formula> A, ensuring strong sneak-path suppression while preserving a wide <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>/<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> ratio. The threshold voltage shifts from −3.0 to −0.6 V, lowering gate-dielectric stress. The resulting TFT successfully electroforms and switches a TiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <i>x</i> </sub> RRAM with a 100 k<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula> window when the gate is <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>, while blocking switching in the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> state. These results demonstrate an effective TFT design for resistive memory integration and emphasize the potential of 1T1R architectures to overcome the conventional memory-compute bottleneck, as memristors enable in-memory computing with high-density operation.