Investigations on Enhancing the Scaling Performance of RingFETs

In this paper, performance optimization of RingFETs through LDD implantation, using corrugated substrate and selective back oxide structure has been demonstrated using numerical simulations. Using 3D TCAD simulations, the device parameters for the inner and outer drain designs are obtained, such as ON current, OFF current, threshold voltage, subthreshold slope, transconductance, and unity gain frequency. LDD implantation improves the performance of the device by reducing the leakage current. SegRingFET, that is, segmented channel RingFET uses corrugated substrate to mitigate scaling problems by providing improved gate control. The impact of LDD in the SegRingFET structure is studied. SELBOX has the advantages of an SOI architecture and also reduces the kink effect that arises due to a floating body. The implications of SELBOX structure on LDD implanted SegRingFET are studied.