A flexible high-performance domain-specific vector RISC-V processor for post-quantum cryptography

A vector-processor architecture based on the RISC-V extended instruction set is proposed and evaluated for the acceleration of post-quantum cryptographic(PQC) algorithms. The core employs an in-order, partially four-way multi-issue pipeline and delivers a significant speed-up over pure-software RISC-V implementations. Unlike previous hardware–software co-designs that target specific PQC schemes, the instruction-set extensions are derived from fine-grained, fixed-point arithmetic primitives; consequently, the same core can speed up current NIST candidates and tolerate future algorithm updates while remaining useful for other cryptographic workloads. The processor was implemented in 28nm SMIC HKE+ process, and post-layout simulations were conducted. Results showed that under primary PQC standards, compared with the state-of-the-art counterparts, it can achieve a reduction in total cycles by 9.1%-12.7%. In terms of stream cipher, block cipher, and hash cipher algorithms, it can achieve 12×-24× performance improvement, which enables it to have higher flexibility in practical application scenarios.