Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance

Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. This study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7-nm fin field effect transistor (FinFET) transistors. Variations in critical dimension (CD) during patterning can alter fin width and spacing, leading to changes in device characteristics. We evaluated device sensitivity using a comprehensive set of test structures and performed technology computer-aided design (TCAD) simulations to model the effects. The results confirm that both nMOS and pMOS devices are sensitive to poly spacing, and nMOS devices exhibit up to a 13% degradation in drive current, whereas pMOS devices show −11% to + 7% variation in drive current and interfin spacing. The dominant mechanism behind these effects is stress modulation, particularly due to changes in the volume and shape of epitaxially grown source/drain (S/D) regions. These findings highlight the critical role of mechanical stress in FinFET performance and underscore the importance of pitch control to minimize variability and optimize device parametric targets.