FSM-Based MBISST Controller Implementation using the March AZ2 Test Algorithm

An efficient on-chip memory testing requires the use of a Memory Built-In Self-Test (MBIST) that applies a low-complexity test algorithm that offers excellent fault coverage, to ensure high test quality at a minimal cost. The March AZ2 algorithm, with 14N complexity, was previously established to balance the fault coverage and test complexity. It was previously implemented in an MBIST controller through an automatic generation process using an Electronic Design Automation (EDA) tool, which limits its customizability and optimization potential. This paper presents the implementation of an MBIST controller that employs the March AZ2 test algorithm and is based on a Finite-State Machine (FSM) architecture. The developed MBIST controller was implemented on a Field-Programmable Gate Array (FPGA) to validate its functionality and fault coverage. A comparison with an equivalent MBIST controller automatically generated using Siemens EDA Tessent MemoryBIST tool demonstrates that the proposed FSM-Based MBIST controller achieves 84% lower circuit area and 32% power consumption, while offering similar fault coverage. ABSTRAK: Pengujian memori atas cip yang cekap memerlukan penggunaan Ujian-Kendiri Terbina-Dalam Memori (MBIST) menggunakan algoritma ujian berkompleksiti rendah dan menawarkan liputan kesalahan yang tinggi, bagi memastikan kualiti ujian baik pada kos minimum. Algoritma March AZ2, dengan kekompleksan 14N, telah diperkenalkan sebelum ini bagi mengimbangi antara liputan kesalahan dan kompleksiti ujian. Ia telah dilaksanakan dalam pengawal MBIST melalui proses penjanaan automatik menggunakan Automasi Reka Bentuk Elektronik (EDA), yang menghadkan tahap kebolehsuaian dan potensi pengoptimuman. Kajian ini membentangkan pelaksanaan pengawal MBIST yang menggunakan algoritma ujian March AZ2, berasaskan seni bina Mesin Keadaan-Terhingga (FSM). Pengawal MBIST yang dibangunkan telah dilaksanakan pada Litar Terpadu-Serba Guna (FPGA) bagi mengesahkan fungsi dan liputan kesalahan. Perbandingan dengan pengawal MBIST yang dijana secara automatik menggunakan Siemens EDA Tessent MemoryBIST membuktikan bahawa pengawal MBIST berasaskan FSM yang dicadangkan mengurangkan keluasan litar sebanyak 84% dan penggunaan kuasa 32% lebih rendah, sambil mengekalkan liputan kesalahan yang sama.