High‐Performance and Energy‐Efficient Sub‐5 nm 2D Double‐Gate MOSFETs Based on Silicon Arsenide Monolayers

ABSTRACT The continuous demand for high‐performance (HP), energy‐efficient transistors is driving research beyond conventional silicon‐based metal‐oxide‐semiconductor field‐effect transistors (MOSFETs), which face critical scaling limits. To address this challenge, new channel materials and device architectures are being explored. Here, we investigate sub‐5 nm double‐gate (DG) MOSFETs based on 2D SiAs using first‐principles calculations combined with the non‐equilibrium Green's function (NEGF) formalism. SiAs monolayers exhibit an indirect bandgap of 1.58 eV and favorable electronic characteristics for device applications. We evaluate key performance metrics, including the on/off current ratio (I on /I off ), subthreshold swing (SS), gate capacitance (C g ), intrinsic delay time (τ), and power–delay product (PDP). Underlap ( UL ) architectures with 1–2 nm extensions enhance device performance, yielding on‐state currents (I on ) up to 1206 µA µm −1 , in line with the International Technology Roadmap for Semiconductors (ITRS) 2028 HP requirements. The SS values (112–142 mV dec −1 ) together with minimized τ and PDP indicate the suitability of SiAs transistors for ultra‐scaled, energy‐efficient technologies. Our findings highlight 2D SiAs as a promising candidate to overcome the scaling challenges of traditional MOSFETs and to advance next‐generation semiconductor devices.