Safe UAV Continuous-Control Architecture Design

Unmanned Aerial Vehicles (UAVs) are often classified as safety-critical systems due to the severe implications a failure might have. Ensuring safety guarantees is therefore paramount in UAV design. This paper introduces a solution to provide safety guarantees during the design of the continuous-control architecture, a critical component. Formal verification (FV) techniques are employed to detect software errors and verify the architecture's ability to meet real-time system requirements. The first verification round utilizes the ESBMC model checker, focusing on individual elements of the architecture, particularly the continuous-control algorithm. The second verification process employs the UPPAAL model checker to conduct a schedulability analysis of the proposed architecture. Finally, a runtime monitoring analysis is performed using the newly developed RMLib tool. This approach was successfully applied in the design process of a UAV, identifying and correcting various design and implementation issues, as detailed in the paper.

Authors

Institutions

Publication Details

Journal
ACM SIGAda Ada Letters
Published
2025-06-01
DOI
https://doi.org/10.1145/3784987.3784989
Primary Topic
Real-Time Systems Scheduling
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Safe UAV Continuous-Control Architecture Design

L. B. Becker, E. F. Broering, H. A. Misson, F. S. Gonçalves et al.
ACM SIGAda Ada Letters
Real-Time Systems Scheduling
article

Safe UAV Continuous-Control Architecture Design

L. B. Becker, E. F. Broering, H. A. Misson, F. S. Gonçalves, L. Cordeiro
article en

Abstract

Unmanned Aerial Vehicles (UAVs) are often classified as safety-critical systems due to the severe implications a failure might have. Ensuring safety guarantees is therefore paramount in UAV design. This paper introduces a solution to provide safety guarantees during the design of the continuous-control architecture, a critical component. Formal verification (FV) techniques are employed to detect software errors and verify the architecture's ability to meet real-time system requirements. The first verification round utilizes the ESBMC model checker, focusing on individual elements of the architecture, particularly the continuous-control algorithm. The second verification process employs the UPPAAL model checker to conduct a schedulability analysis of the proposed architecture. Finally, a runtime monitoring analysis is performed using the newly developed RMLib tool. This approach was successfully applied in the design process of a UAV, identifying and correcting various design and implementation issues, as detailed in the paper.

ACM SIGAda Ada LettersVol. 45(1)
University of Manchester (GB), Universidade Federal de Santa Catarina (BR), Polytechnique Montréal (CA), Instituto Federal de Educação, Ciência e Tecnologia de Santa Catarina (BR)
Openalex Percentile: Top 29%
Real-Time Systems Scheduling
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Safe UAV Continuous-Control Architecture Design — L. B. Becker, E. F. Broering, et al. · ACM SIGAda Ada Letters (2025) | TGRS Research Map | TGRS