Near-zero hysteresis van der Waals MnAl2S4 field-effect transistors with low minimal threshold voltage degradation and high thermal stability

The integration of high-quality, ultrathin van der Waals (vdW) dielectrics with 2D semiconductors remains a critical bottleneck in the development of reliable, ultra-scaled field-effect transistors (FETs). Here, we report a comprehensive study of MoS₂-based FETs employing layered rhombohedral MnAl₂S₄ as the gate insulator, a previously unexplored vdW dielectric that can be isolated down to the monolayer limit. Devices fabricated in both top-gated (TG) and bottom-gated (BT) configurations exhibit excellent electrical performance, featuring low gate leakage, minimal hysteresis ( < 2 mV) under high electric fields up to 11 MV cm^-1 across a wide range of gate voltage sweep rates (0.001-10 Vs^-1). We observed a consistent counterclockwise hysteresis and an anomalous bias temperature instability (BTI), possibly caused by the diffusion of Mn interstitials and S vacancies formed inside the MnAl₂S₄ film during growth. Notably, we show that threshold voltage degradation at high temperatures was observed to be negligible, and hysteresis dynamics and very small BTI are reproducible over a long time, demonstrating the high reliability of our devices. In addition, the vdW interface between MnAl₂S₄ and MoS₂ in our device is of good quality and is expected to provide a small density of insulator defects, a promising gate dielectric for reliable 2D devices.