Design of improved structures for multi-bit data addition devices in binary codes of the Rademacher theoretical-numerical basis

This study investigates the process of designing multi-bit adders based on an improved element base of their components in binary codes of Rademacher theoretical-numerical basis. The task addressed relates to the fact that the known element base of modern single-bit adders does not make it possible to achieve the minimax characteristics of sum formation and carry-save efficiency in their structures in 1 micro cycle. The improved element base of single-bit adders has been built on the basis of the «Exclusive AND» logic element, which has low hardware complexity and high speed of output signal formation. Improved architectural solutions for full and half single-bit binary adders with minimax characteristics of hardware and time complexity in structures of multi-bit adders of various types have been applied. The system characteristics of microelectronic structures of multi-bit adders of various types based on full and half single-bit binary combinational adders with direct, inverse, and paraphase inputs and outputs have been investigated. As a result, it has been theoretically established and practically confirmed that multi-bit adders based on an improved element base have 2 times less hardware complexity and 6 times higher speed. The structure of a cascaded n-bit fast adder has been designed, which has a speed 1.8 times higher than that of the known implementation. Using the VHDL hardware description language and Vivado CAD, a 64-bit cascade adder was modelled and synthesized on FPGA, which has twice the speed of the known adder. The designed multi-bit Rademacher basis adders are applicable to statistical, correlation, and entropy analysis tasks, video image processing, image recognition, as well as various artificial intelligence tasks