Erasing by Hot Hole Injection in eSTM™ device: comprehension and optimization

Abstract In this paper, we present an experimental study of a new method based on Hot Hole Injection (HHI) for the embedded Select in Trench Memory (eSTM™) cell. An in-depth investigation of the floating implant provides insight into the erase mechanism. Electrical characterizations across the wafer reveal two distinct cell behaviors. The objective is therefore to identify the origin of these behaviors. It is demonstrated that no wafer-level effect is involved. Instead, this variability comes from process fluctuation of the Adjust threshold voltage (AdV T ) dose and the Lightly Doped Drain (LDD) depth. To optimize this new erase operation, a set of electrical characterizations are carried out on various process splits of the device. This enables the identification of a better trade-off that increases the cell’s erase probability. However, the optimized device has erasure failures. Future work should aim to achieve completely reliable operation (i.e. 100% of the expected behavior) while reducing the current consumption of the cells.

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Publication Details

Journal
Japanese Journal of Applied Physics
Published
2026-01-09
DOI
https://doi.org/10.35848/1347-4065/ae3574
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
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article

Erasing by Hot Hole Injection in eSTM™ device: comprehension and optimization

M. Mantelli, Thibault Kempf, S. Niel, Francesco La-Rosa et al.
Japanese Journal of Applied Physics
Integrated Circuits and Semiconductor Failure Analysis
article

Erasing by Hot Hole Injection in eSTM™ device: comprehension and optimization

M. Mantelli, Thibault Kempf, S. Niel, Francesco La-Rosa, Arnaud Régnier, P. Canet, Celine Belabbas, Vincenzo Della Marca
article en

Abstract

Abstract In this paper, we present an experimental study of a new method based on Hot Hole Injection (HHI) for the embedded Select in Trench Memory (eSTM™) cell. An in-depth investigation of the floating implant provides insight into the erase mechanism. Electrical characterizations across the wafer reveal two distinct cell behaviors. The objective is therefore to identify the origin of these behaviors. It is demonstrated that no wafer-level effect is involved. Instead, this variability comes from process fluctuation of the Adjust threshold voltage (AdV T ) dose and the Lightly Doped Drain (LDD) depth. To optimize this new erase operation, a set of electrical characterizations are carried out on various process splits of the device. This enables the identification of a better trade-off that increases the cell’s erase probability. However, the optimized device has erasure failures. Future work should aim to achieve completely reliable operation (i.e. 100% of the expected behavior) while reducing the current consumption of the cells.

Japanese Journal of Applied PhysicsVol. 65(3)
Centre National de la Recherche Scientifique (FR), Université de Toulon (FR), STMicroelectronics (France) (FR)
Openalex Percentile: Top 94%
Integrated Circuits and Semiconductor Failure Analysis
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