Optimized DPD Design with Peak-Detection-Based Loop-Delay Estimation for Power Amplifier Linearization: Addressing High–Low Power Distortion via Memory-Clustering Biased Polynomial

This paper proposes an optimized digital predistortion (DPD) framework. Firstly, a peak-detection-based loop-delay estimation is developed by leveraging the unique peak distribution of Orthogonal Frequency Division Multiplexing (OFDM) signals. It reduces the required number of samples to as small as two without compromising estimation accuracy. Then, a Biased Memory Polynomial (BMP) model is proposed for power amplifier modeling. It addresses low-power inaccuracies caused by circuit imperfections (e.g., DC offsets) by adding a bias term to conventional memory polynomials, improving linearization accuracy in low-power regime. Last, to improve the accuracy of coefficient derivation, Memory-Clustering Biased Memory Polynomial (MBMP) is proposed by grouping signals into clusters based on memory-attenuated input vectors and processing them with dedicated sub-models. It improves linearization accuracy in high-power regime. Experimental results demonstrate that the MBMP model reduces normalized mean square error (NMSE) by 16.12 dB, and reduces adjacent channel power ratio (ACPR) by about 12 dBm compared to conventional MP.