Design of low power and high speed approximate multipliers utilizing current mode 4 to 2 compressors based on CNTFET technology

The main objective of this paper is to design low-power, high-speed approximation multipliers suitable for fault-tolerant applications in image and signal processing, aiming to minimize hardware cost, power consumption, and latency while maintaining acceptable accuracy for human-perceivable outputs. The innovation of the proposed technique lies in the innovative integration of flow-state logic with 4:2 dual-purpose compressors based on 7 nm CNTFET technology, which introduces six new compressor types that use adjustable threshold voltages, direct current summing without threshold detectors, and improved noise margins to significantly reduce sensitivity to process voltage–temperature (PVT) variations. This technology is up to 30–50% less vulnerable compared to previous CMOS and FinFET-based designs. These compressors are used to implement two types of 8 × 8 Dada multipliers: one with uniform approximation compressors and the other with truncated least significant bits and combined exact-approximation columns. Simulation results in HSPICE and MATLAB show that the optimized design achieves a power consumption of 0.52 mW, a latency of 1.88 ns, and a PDP of 0.97 pj, while maintaining comparable error rates and improving image quality metrics, such as MSSIM by 62% (from 59.61 to 96.83%) and PSNR by 15–20% compared to existing multipliers in the image multiplication function.