Effect of Gate Length Relative to Recess Coverage on the Performance of Enhancement‐Mode β‐Ga ₂ O ₃ MOSFETs

ABSTRACT This study examines gate‐length engineering in recessed‐gate enhancement‐mode β‐Ga 2 O 3 metal‐oxide‐semiconductor field effect transistors on c‐plane sapphire, with emphasis on extending the gate to fully cover the etched recess. All epitaxial layers were grown simultaneously, and devices were fabricated using the same process flow, with gate length as the only design variable. Devices with a 3 µm gate partially cover the recessed region, while those with a 5 µm gate span the entire recess. Electrical measurements show that full recess coverage removes ungated segments, improves electrostatic control, and lowers series resistance. A significant threshold voltage shift, from 7.7 V to 2.4 V, was observed as gate coverage increased from 3 to 5 µm, further validated through TCAD simulations. Consequently, the specific on‐resistance decreases from 1.85 to 1.04 kΩ.mm, and the drain current on/off ratio improves from 1.8 × 10 7 to 1.6 × 10 8 , with normally‐off operation maintained. Capacitance‐voltage analysis further reveals that the field‐effect mobility increases from 2.06 to 5.29 cm 2 /V·s, while the channel electron concentration decreases from 8.2 × 10 16 to 5.4 × 10 16 cm −3 . These results demonstrate that complete recess coverage is an effective approach to enhance device conduction and subthreshold behavior without altering the fabrication process.