A Digitally Phase‐Programmable Three‐Stage Amplifier With Fractional Miller Compensation Capacitor Utilizing the SFG Investigated Cascade Transformation Graph Rules

ABSTRACT This paper examines the design of a digitally phase‐programmable three‐stage amplifier, presenting the design process primarily through signal flow graph manipulation. Specifically, a digitally phase‐programmable (DPP) dual active‐capacitive‐feedback compensation (DACFC) amplifier architecture is derived by applying graph transformation rules and graph algebra–based design analysis, starting from the signal flow graph of a DACFC amplifier. The compensation capacitor or the phase margin (PM) of the proposed amplifier is made variable by adjusting the digital input code vector and the value of k placed in the feedback path. Depending on the required value of the PM, this technique enables a three‐stage amplifier with programmable compensation capacitor. This technique, using the cascade graph rule, simplifies the edge representing the compensation capacitor in the feedback path. This simplification increases the PM while reducing the chip area occupied by the compensation capacitor (compared to the non‐digital compensation capacitor amplifier), especially when k > 1. It has demonstrated effective and favorable results. After mapping the amplifier from the graph domain to the circuit domain, the DPP‐DACFC is simulated in 0.18‐μm CMOS standard technology. When the capacitive load is C L = 500 pF, the compensation capacitor is 2.4 pF, and the k value is set to 1.17 at a unity gain frequency of 3.585 MHz; a PM of 84.7° is achieved. The power consumption is 301 μW, and the DC gain exceeds 100 dB. The average slew rate of 3.09 V/μs and settling time of 0.465 μs are obtained when the proposed amplifier is configured in a unity gain non‐inverting configuration. Under a load capacitance of C L = 1250 pF, the amplifier maintains a PM of 57°.