Optimizing the performance of wide-bandgap CZTS solar cells: influence of heterojunction structure, buffer thickness and doping concentration

Over the past decade, the efficiency of CZTSSe solar cells has been significantly improved, particularly in narrow-bandgap CZTSSe solar cells. The formation of a "spike" structure at the CdS/CZTSSe heterojunction interface is considered as the main reason for the enhancement of narrow-bandgap CZTSSe devices' performance. Although the ideal efficiency of wide-bandgap CZTS solar cells is higher, their actual performance lags behind that of narrow-bandgap CZTSSe devices. A critical limiting issue is the severe recombination occurring at the heterojunction interface of wide-bandgap CZTS solar cells. Some studies indicate that the unfavorable "cliff" structure is the main factor causing its heterojunction interfacial recombination. This study conducts an in-depth analysis through simulation to investigate the effects of different heterojunction structures, doping concentrations and thicknesses of the CdS buffer layer on heterojunction interfacial recombination and device performance. The aim is to verify whether the "spike" structure is also beneficial for the improvement of wide-bandgap CZTS device performance, as well as to study the impact of these combined features on the device performance. The simulation results reveal that the optimal heterojunction structure is related to the doping concentration and thickness of the CdS buffer layer. When the CdS layer doping concentration is low and its thickness is thin (∼10 nm), a "flat" or "spike" heterojunction structure should be employed to reduce interfacial recombination. Conversely, when the CdS layer doping concentration is high with a thicker thickness (∼50 nm), the interfacial recombination of the heterojunction becomes less significant. In such cases, an optimal heterojunction structure would exhibit a weak "cliff" structure, which can not only reduce interfacial recombination but also suppress the formation of an interfacial barrier, thereby significantly improving the device performance.