Design and Implementation of an Air Conditioner Using Finite State Machine (FSM)

Abstract— This project uses a standard ASIC design flow and the following course materials: Cadence Genus for synthesis, Cadence Innovus for physical implementation and signoff, and ModelSim for RTL functional verification to implement the Finite State Machine (FSM) based Air Conditioner controller as outlined in the project proposal. The work performs placement, clock-tree synthesis, routing, and physical verification to create a layout-ready design after confirming the FSM's functional behavior at the RTL level and synthesizing the validated RTL to a gate-level netlist within the given SDC restrictions. The report details the approach taken, provides a narrative analysis of the findings, including timing and physical verification data, and provides a project summary at the end. The design inputs, SDC limitations, and necessary outputs adhere to the guidelines given in the course.