Generation of Synthesizable Verilog Code From Natural Language Specifications

This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language models with parameter-efficient fine-tuning—specifically, Low-Rank Adaptation and Quantized Low-Rank Adaptation—together with a specialized corpus of specification–code pairs that covers common design patterns and varying task complexity. The pipeline includes automated compilation, simulation, and synthesizability checks to ensure that outputs are both syntactically correct and suitable for downstream tool flows. Evaluation is performed using the pass-at-k metric on the standardized VerilogEval benchmark. The fine-tuned models substantially improve functional correctness over untuned baselines, achieving pass-at-k of up to 0.88 while markedly reducing both syntax and logic errors. The results indicate that reliable Verilog code generation from natural language can be achieved under constrained compute budgets; in our setup, effective training and inference remained feasible on a single graphics processing unit. Beyond empirical gains, the method demonstrates practical value for design automation by shortening iteration cycles and lowering the effort needed to move from textual requirements to synthesizable hardware modules. Overall, the findings support the use of large language models, paired with targeted data and validation, as a viable pathway for Verilog code generation and for accelerating the development of complex digital devices.