A resource-constrained CNN accelerator for real-time license plate character recognition on FPGA platforms

Convolutional Neural Networks (CNNs) are widely used in Automatic License Plate Recognition (ALPR) systems for Optical Character Recognition (OCR). Still, their computational cost often restricts deployment on edge devices. This work presents an 8-bit quantized CNN with a hardware-oriented dataflow designed specifically for OCR of Mercosur and Brazilian license plates. The model was trained using quantization-aware techniques and implemented on two FPGA platforms from different vendors, Altera Cyclone V and AMD Zynq UltraScale+, using the same VHDL architecture. The Zynq UltraScale+ implementation achieves 97.1% OCR accuracy, 2.12 ms latency, and 922 FPS in pipelined mode, while the Cyclone V version delivers 458 FPS with reduced BRAM and DSP usage. Energy measurements show 1.62 mJ per inference on Zynq UltraScale+ and 3.32 mJ on Cyclone V, confirming suitability for low-power, real-time ALPR. The results demonstrate that a portable 8-bit design can maintain accuracy comparable to that of floating-point models while achieving substantial gains in throughput and energy efficiency across heterogeneous FPGA devices. • A novel 8-bit CNN hardware accelerator for Optical Character Recognition (OCR) of Mercosur and Brazilian license plates is proposed. • The architecture is based on a modified LeNet-5 model, optimized for low-cost and resource-constrained FPGA implementations. • The system was implemented and validated on two platforms, Altera Cyclone V and AMD Zynq UltraScale+, demonstrating portability and scalability across FPGA vendors. • The accelerator achieves 97.1% accuracy, 2.12 ms latency, and 922 FPS on the Zynq UltraScale+, and 458 FPS on the Cyclone-V, with up to 90% lower energy per inference compared to prior FPGA solutions. • A complete hardware–software co-design workflow was adopted, including dataset preparation (UFPR-ALPR, SATTRA), 8-bit quantization, and VHDL implementation for real-time ALPR systems. • The proposed accelerator maintains high accuracy and efficiency while reducing resource utilization to under 20% of comparable FPGA designs, enabling edge deployment in low-power, real-time traffic monitoring.