Schakelingsfysica van FeFET-geheugenapparaten met een oxide-halfgeleiderkanaal

The rapid growth of AI training and edge inference raises stringent requirements on memory latency, bandwidth, energy, and 3D integrability. HfO2-based Ferroelectric Field-Effect Transistors (FeFETs) offer a path to low-latency, non-volatile memory cells compatible with monolithic 3D integration for high density. Employing an oxide-semiconductor IGZO channel enables a true metal-ferroelectric-semiconductor stack with reduced charge trapping and BEOL compatibility. However, the scarcity of holes in wide-bandgap IGZO challenges an efficient erase operation, which requires positive charges to balance negative polarization. This thesis elucidates charge-balance mechanisms during ferroelectric switching, and develops device designs that stabilize the switching and deliver high endurance. We first build an electrostatic description of ferroelectric switching in the metal/ferroelectric/IGZO stack that accounts for the sources of positive charge in the absence of holes. Partially ionized donor states are identified as the positive screening charges that balance negative polarization during erase. Through switching kinetics evaluations on ferroelectric capacitors and transistors, we find that erase proceeds more slowly than program. These results reveal that the time needed to complete erase is the key bottleneck for low-latency IGZO-channel FeFETs. On planar back-gated FeFET devices, we implement gate-stack optimization to stabilize the cycling, and accelerate erase in short-channel devices due to the source/drain fringing fields. The extrinsic breakdown is suppressed with source/drain area scaling, and IGZO-channel composition tuning allows for enlarging the memory window and stabilizing the threshold voltage. Together, these strategies enable microsecond-scale erase and endurance up to 1e10 cycles. Moving from planar to 3D devices, we demonstrate vertically integrated IGZO-channel FeFET cells connected in NAND strings. The devices exhibit ferroelectric memory window yet show the expected slow erase in long-channel strings where the fringing field is weak. To address the slow-erase issue in long-channel FeFETs, we propose a dual-gate structure that strengthens electrostatic control over the floating IGZO channel. Measurements and simulations confirm faster and more complete switching in dual-gate FeFETs even at large channel lengths, indicating the feasibility of fast-erasable 3D IGZO-channel FeFETs through back-gate control. Overall, this work advances IGZO-channel FeFET memory from physical understanding to device design across planar and 3D forms. It provides fundamental insights, device-engineering guidelines, and integration directions that support low-latency operation, reliable cycling, and practical 3D implementation of IGZO-channel FeFET memories.