Simulation Modeling and Investigation of Silicon on Insulator Devices

Abstract:As transistor scaling reaches the 5 nm node, conventional bulk MOSFETs suffer from severe short-channel effects (SCE), including high leakage current and poor gate control. This research utilizes Silvaco TCAD ATLAS to design and compare the performance of 5 nm Partially Depleted (PDSOI) and Fully Depleted (FDSOI) Silicon-on-Insulator devices. The PDSOI architecture, which relies on high channel doping of 1 × 10^18 cm^-3 and surface inversion, achieves a peak intrinsic speed of 4.2 THz and an electron mobility of ≈ 400 cm^2/V·s. However, the simulation indicates a subthreshold swing of 93.97 mV/decade and a threshold voltage (Vth) of 0.554 V for the PDSOI device. In contrast, the FDSOI device utilizes an ultra-thin 1.3 nm body and volume inversion to provide superior electrostatic control. The FDSOI variant demonstrates a higher Vth of 0.665 V and an improved electron mobility of ≈ 405 cm^2/V·s, despite a subthreshold swing of 118.2 mV/decade. Based on these performance metrics, PDSOI is best suited for high-speed RF and radar applications where intrinsic switching speed is critical. Conversely, FDSOI is identified as the optimal choice for high-density digital logic (CPUs/GPUs) and low-power IoT devices due to its reliable switching behavior and superior energy efficiency at the 5 nm node.