A Nano-Complementary Metal-Oxide-Semiconductor Low-Power VLSI Security Architecture with Future Optoelectronic Sensor Integration for IoT Networks

A nano-CMOS-based low-power VLSI architecture is presented for enhanced malicious and residual node detection in mobile ad hoc networks (MANETs) and IoT-enabled wireless sensor systems. The proposed Low-Power VLSI Architecture (LP-VLA) functions as a dedicated hardware security engine, integrating a three-stage adaptive detection pipeline comprising trust evaluation, anomaly scoring, and residual-energy degradation analysis. To achieve energy efficiency at scaled technology nodes, the architecture employs bit-serial computation, clock gating, and dynamic voltage–frequency scaling (DVFS) to minimize switching activity and leakage power. Implemented using 65-nm nano-CMOS technology, the design occupies 0.42 mm 2 and consumes 8.7 mW at 100 MHz, achieving a 62% power reduction compared with FPGA-based security implementations. Comprehensive post-layout experimental evaluation demonstrates a malicious node detection accuracy of 96.8%, a low false-positive rate of 2.7%, and a residual node prediction precision of 94.2%, with an evaluation latency of 0.83 μ s per node. The compact nanoelectronic architecture enables scalable deployment in dense IoT and cyber–physical systems and provides a feasible pathway for future integration with optoelectronic sensing modules, supporting unified security and perception at the hardware level.