Investigating non-volatile memory architectures for neuromorphic systems with CMOS spike-timed synaptic plasticity

Learning is crucial for the brain’s ability to adapt to changing conditions. We suggest a collection of novel neuromorphic construction circuits, adjustable synapse circuits, and CMOS Spike Based Driven Synaptic Plasticity (CSBDSP) erudition algorithm devices during an attempt to generate compressed and physiologically realistic SCNNs even as limiting power Dissipation. We make two contributions to the learning rule implementation for large-scale extended neuromorphic systems. A novel OxRAM-based Non-Volatile CMOS SRAM (NVSRAM) device is introduced in this article. The 9T-SRAM architecture, especially with the integration of Ox-RAM (Oxide Resistive RAM) technology, presents improvements compared to conventional 6T SRAM and other SRAM types by enhancing stability, minimizing leakage current, and optimizing read/write performance. Comparing SRAM and NVSRAM’s performance at the memory and cell levels is advised. DG FINFET (Double gate Fin Shaped Field Effect Transistor) approaches have been used to lower the SRAM cell’s power consumption. According to the findings, the SRAM cell based on DG FINFETs performs the best in form of power Dissipation. Design impenetrability, leakage current, and power consumption are amongst the many factors that are compared. The circuits under description are constructed at 180 nm and 90 nm using high voltage CMOS technology.