Low-Power VLSI Design for Compressed Sensing-Based Medical Image Fusion

Compressed sensing (CS) has emerged as a promising technique for reducing data acquisition rates while maintaining high-fidelity reconstruction in medical imaging. However, implementing CS algorithms in hardware often incurs significant power and area overheads, limiting their suitability for portable and real-time medical systems. This paper presents a low-power VLSI design for compressed sensing-based medical image fusion, integrating optimized sensing matrices, sparse transformation, and reconstruction modules into a unified hardware framework. The proposed architecture employs adaptive thresholding and approximate arithmetic logic to minimize dynamic power consumption while maintaining high structural similarity (SSIM > 0.96) and peak signal-to-noise ratio (PSNR > 45 dB) across multimodal image datasets (CT–MRI and MRI–PET). A parallel sparsity-driven reconstruction engine based on modified Orthogonal Matching Pursuit (OMP) achieves up to 38% reduction in computational latency compared with conventional architectures. Fabricated on a 45-nm CMOS process, the design achieves 26% lower power dissipation and 22% area efficiency improvement relative to existing CS-fusion VLSI implementations. Experimental results validate that the proposed system provides a high-performance, energy-efficient solution for real-time medical image fusion in point-of-care and wearable diagnostic devices.