IMPACT OF MULTI-PHASE, MULTI-FREQUENCY CLOCKING ON DELAY AND SUPPLY NOISE IN MODERN CMOS PROCESSORS

The supply noise and latency of modern CMOS processors are investigated in this work to see how multi-phase, multi-frequency clocking influences these characteristics. The increasing demand for improved performance and energy efficiency in semiconductor devices has led to the development of optimal clocking algorithms, which are becoming increasingly important components. In the beginning, research studied about how CMOS processors are now having a hard time meeting the ever-increasing needs for performance while consuming a very little amount of power. The number of research that have been conducted in the past on the impacts of delay and supply noise on single-phase, multi-phase, and multi-frequency clocking operations has been rather limited. Our proposed method makes use of cutting-edge CMOS process models and advanced simulation tools to carry out a comprehensive study. This is done to bridge the gap that has been identified. To determine the effects that different clocking configurations have on delay and supply noise across a spectrum of frequencies and phase relationships, these configurations are subjected to stringent testing. The findings shed insight on the costs and benefits of multi-phase, multi-frequency clocking, which were previously unknown. During our research, research discovered that certain configurations drastically cut down on supply noise while simultaneously raising latency. This could be an effective method for improving CPU performance in general. In addition to this, the study identifies specific instances in which the associated costs and benefits need to be carefully considered.