Automatic tuning based on hardware performance counters and machine learning

This paper presents a Machine Learning (ML) methodology for automatically tuning parallel applications in heterogeneous High Performance Computing (HPC) environments using Hardware Performance Counters (HwPCs). The methodology addresses three critical challenges: counter quantity versus accessibility tradeoff, data interpretation complexity, and dynamic optimization needs. The introduced ensemble-based methodology automatically identifies minimal yet informative HwPC sets for code region identification and tuning parameter optimization. Experimental validation demonstrates high accuracy in predicting optimal thread allocation ( > 0.90 K-fold accuracy) and thread affinity ( > 0.95 accuracy) while requiring only 4–6 HwPCs. Compared to search-based methods like OpenTuner, the methodology achieves competitive performance with dramatically reduced optimization time. The architecture-agnostic design enables consistent performance across CPU and GPU platforms. These results establish a foundation for efficient, portable, automatic, and scalable tuning of parallel applications.

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Publication Details

Journal
Future Generation Computer Systems
Published
2025-12-31
DOI
https://doi.org/10.1016/j.future.2025.108358
Citations
1
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
2.27
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article

Automatic tuning based on hardware performance counters and machine learning

Jiří Filipovič, Jordi Alcaraz, Anna Sikora, Eduardo César et al.
1 citations
Future Generation Computer Systems
Parallel Computing and Optimization Techniques
2.27
article

Automatic tuning based on hardware performance counters and machine learning

Jiří Filipovič, Jordi Alcaraz, Anna Sikora, Eduardo César, Suren Harutyunynan Gevorgyan
article en
1 citations

Abstract

This paper presents a Machine Learning (ML) methodology for automatically tuning parallel applications in heterogeneous High Performance Computing (HPC) environments using Hardware Performance Counters (HwPCs). The methodology addresses three critical challenges: counter quantity versus accessibility tradeoff, data interpretation complexity, and dynamic optimization needs. The introduced ensemble-based methodology automatically identifies minimal yet informative HwPC sets for code region identification and tuning parameter optimization. Experimental validation demonstrates high accuracy in predicting optimal thread allocation ( > 0.90 K-fold accuracy) and thread affinity ( > 0.95 accuracy) while requiring only 4–6 HwPCs. Compared to search-based methods like OpenTuner, the methodology achieves competitive performance with dramatically reduced optimization time. The architecture-agnostic design enables consistent performance across CPU and GPU platforms. These results establish a foundation for efficient, portable, automatic, and scalable tuning of parallel applications.

Future Generation Computer SystemsVol. 179
Universitat Autònoma de Barcelona (ES), University of Oregon (US), Masaryk University (CZ)
Openalex Percentile: Top 9%
Parallel Computing and Optimization Techniques
2.27
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Automatic tuning based on hardware performance counters and machine learning — Jiří Filipovič, Jordi Alcaraz, et al. · Future Generation Computer Systems (2025) | TGRS Research Map | TGRS