Configuration Information Generation for Reconfigurable Decoupled Access-Execute CGRA

Coarse-grained reconfigurable architecture (CGRA) has increasingly begun to be used across a wide range of edge computing due to its characteristics, such as high performance, low power consumption and versatility. Versatility is usually considered an important design principle of traditional CGRA architectures during architectural design. On the other hand, the traditional CGRA architecture must take into account the execution of control flow-intensive programs. LUNA, an AI chip with features of separate memory access, computation and reconfigurable hardware connections toward edge neural network computing, can handle vector, matrix, and convolution operations uniformly, which poses great challenges to the generation of configuration information. This paper aims to research the configuration information compilation and generation methods for the new CGRA architecture, and design a counter array allocation strategy based on loop analysis to solve the configuration information generation problem of memory access addresses. Additionally, this paper proposes a hardware connection generation method to address the configuration information generation problem of reconfigurable hardware connections. The hardware configuration information generation method presented in this paper, which is proven to be effective through testing with vector, matrix and other datasets, is said to achieve a performance of over 95% as compared to hand-optimized assembly.