Latency-Optimal Quantum Circuits for IoT Networks

Future IoT networks will demand increasingly lower latency for transmitting mission-critical information while simultaneously adopting quantum technologies to enhance security and accelerate information processing. This survey reviews the state-of-the-art in latency-optimal quantum circuit design, focusing on minimizing circuit latency without sacrificing essential functionality. The space is primarily allocated to the network level aspects, exploring balance between the network latency and the energy consumption, programmability and cost, while establishing a proper interface with the problems that should be delegated to the practical design carried on by circuit developers. Section I analyzes how aggressive latency reduction constrains the use of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">universal</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reversible</i> gates—both of which tend to increase circuit depth (latency). Universal gates enable programmability, while reversible gates reduce energy dissipation, yet both can extend circuit latency. Aware of these trade-offs, Section II discusses latency-optimal design methodologies and their implementation aspects. Next we discuss exact minimization of quantum circuits, presenting quantitative improvements. For instance, controlled-T gate implementations demonstrate reductions from 15 → 9 T gates (compression = 15/9), 16 → 12 CNOT gates (compression = 16/12), and 9 → 5 T-latency (compression = 9/5). Similarly, for a 1-bit full adder, reductions include 14 → 8 T gates (14/8), 12 → 10 CNOT gates (12/10), 4 → 2 H gates (2), and 8 → 2 T-latency (4).