Spatio-Temporal Characterization of Diurnal Noise in Superconducting Quantum Processors

This document presents Version 2.0 of a simulation study investigating diurnal noise patterns in superconducting quantum processors using the HS⁰ temporal phase framework. It includes a detailed correction notice for numerical claims made in Version 1.3 (DOI: 10.5281/zenodo.17900332), which were found to be non-reproducible and have been revised downward. For a simulated 127-qubit chip with a 2.6% diurnal amplitude, this study models spatially-varying thermal lag and evaluates phase-aware correction, showing a simulated drift reduction of ~6.7× and a gate fidelity improvement of ~1.8%. All results are from numerical simulation; experimental validation on real hardware is identified as the critical next step. This version supersedes the previous one and serves as a corrected technical reference for the HS⁰ framework's application to noise mitigation. Complete simulation code is provided as supplementary material.