Wideband Simultaneous IM ₂ and IM ₃ Cancellation in FDSOI Resistive Step RF Attenuators

This article presents a wideband resistive step RF attenuator implemented in 22-nm fully depleted silicon-on-insulator (FDSOI) CMOS technology with simultaneous second- and third-order intermodulation (IM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and IM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>) distortion cancellation. We propose a back-gate equalizer (BE) switch topology that converts even-order distortion into odd-order distortion, enabling simultaneous cancellation of the converted distortion and the third-order distortion at the attenuator output. This results in a highly linear and controllable attenuator. A five-step T-attenuator, including a bypass mode, is implemented, occupying 0.0066 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. An insertion loss (IL) of 1.7 dB in bypass mode is observed for both the BE and a reference (Ref.) design. Return loss (RL) remains better than 10 dB up to 10GHz for all settings, except in bypass mode, where it is better than 10 dB up to 7GHz. The measured IIP<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is approximately +30 dBm for both designs, while IIP<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ranges from +60 to +80 dBm for the BE design and around +50 dBm for the Ref. design. An improvement of up to 20 dB in IM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is observed for the BE design compared to the Ref. design. Compared to prior work, this work also introduces a refined design strategy for IM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> distortion cancellation and several other circuit-level optimizations. The demonstrated IIP<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and IIP<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> performance makes the attenuator designs well-suited for today’s high-linearity RF front-ends in highly integrated systems-on-chip (SoC).