CNTFET-based hybrid approximate multiplier design with optimized compressors for error-resilient image processing and enhanced power-delay efficiency

• A CNTFET-based hybrid approximate multiplier is designed using optimized 4:2 and 5:2 compressors to reduce power, delay, and hardware complexity. • The design achieves power savings (0.268 µW), reduced delay (19.3 ps), and a low PDP (6.2 fJ) compared to existing CMOS and approximate multipliers. • An 8 × 8 Dadda-based approximate multiplier demonstrates 7.95 µW power, 0.315 ns delay, and a compact PDP of 2.50 fJ in Cadence simulations. • Application-level validation shows high image quality (PSNR 54.23 dB, SSIM 98.5%), confirming suitability for error-resilient image processing. Carbon Nanotube Field-Effect Transistors (CNTFETs) have emerged as a strong alternative to conventional CMOS technology due to their superior electrical properties, including high carrier mobility, ballistic transport, and scalability at nanoscale dimensions. At the same time, approximate computing offers a practical approach to improving energy efficiency in error-tolerant applications such as image processing. This paper presents the design and implementation of a CNTFET-based hybrid approximate multiplier that integrates optimized 4:2 and 5:2 compressors. The proposed compressors are carefully redesigned with simplified logic, eliminating redundant carry-in dependencies to achieve reduced transistor count, lower power consumption, and improved delay performance. These compressors are incorporated into a Dadda multiplier framework to form the hybrid multiplier, where approximation is selectively applied in less significant bit positions to balance efficiency and accuracy. The design is modeled and simulated in Cadence Virtuoso using the Stanford 32 nm CNTFET model, and its performance is evaluated in terms of power, delay, power-delay product (PDP), and hardware complexity. To validate application-level effectiveness, the multiplier is applied to image processing tasks, and the output quality is assessed using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM). Simulation results demonstrate that the proposed design achieves substantial improvements over CMOS-based and existing approximate multipliers, offering reduced power-delay product while maintaining high perceptual quality in processed images. These findings establish CNTFET-based approximate multipliers as a promising solution for next-generation low-power, high-performance, and error-resilient computing systems.