Common-Mode Voltage Elimination and Zero-Sequence Circulating Current Reduction of Parallel Back-to-Back Converters

Parallel back-to-back converters are highly demanded in many high-power applications such as adjustable speed drive (ASD) systems, which reduce harmonics and improve the power factor and reliability compared to single two-level converters. It is evident that common-mode voltage (CMV) is the root cause of many challenges in ASD systems, such as shaft voltage and bearing damage, which may reduce equipment lifespan. On the other hand, Zero Sequence Circulating Current (ZSCC) leads to an additional current of switches which increases power loss and decreases the current capacity of converters. Simultaneous reduction of these two critical issues has to be considered in any switching strategy. In this regard, this paper presents a switching strategy based on a modified three-level space vector modulation scheme, which completely eliminates the common-mode voltage (CMV = 0 V). Moreover, the proposed switching sequence keeps the ZSCC within a low-amplitude and fully symmetric ripple, ensuring controlled circulating-current behavior without requiring any additional hardware. The method also generates a three-level line voltage and achieves an input-current THD of 3.92%. The simulation and experimental results confirm the effectiveness of the proposed approach.