A 60-GHz Current Combining Class-AB Power Amplifier in 22 nm FD-SOI CMOS

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power (Psat) of 20.2 dBm, and a maximum large-signal gain (Gmax) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes.